The invention relates to a circuit configuration for load-relieved switching having a bridge circuit with at least two-controllable power switches, whose controlled paths are arranged in series with one another and between a first and a second supply potential. The circuit configuration has a drive circuit for driving the power switches. The circuit configuration also has an inductive element that is connected to the output terminals of the bridge circuit.
The article by Leo Zaro et al. xe2x80x9cHigh-Voltage MOSFET Behavior in Soft-Switching Converters: Analysis and Reliability Improvementsxe2x80x9d, in Proceedings INTELEC, 1999, pages 30-40, describes a generic circuit for voltage-relieved switching that is designed as a full-bridge circuit with four power switches.
In power switches, it is possible, in principle, to distinguish between two different types of power loss. First, there is the power loss during the xe2x80x9con phasexe2x80x9d, during which the power switch is switched on or controlled at a low impedance. These losses essentially result from the voltage that is dropped as a result of a current flow in the channel region of the semiconductor switch. Second, there also exist switching losses that are caused by the reciprocal switch-on and -off operation of the power switch, that is to say when a high current density and a high voltage are simultaneously present at the power switch. However, these losses are incurred only during very short time intervals during switch-on and during switch-off. However, as the switching frequency rises and/or as the power to be switched increases, these switching-dictated losses increasingly gain in importance for the total power loss balance.
Therefore, development turns toward circuit concepts that reduce such switching losses by a suitable choice of the switching conditions. One such concept is what is referred to in the relevant technical literature as xe2x80x9cZero Voltage Switchingxe2x80x9d (ZVS). The corresponding circuits are also referred to as resonant circuits or as circuits for zero voltage or voltage-relieved switching. In the case of such circuit configurations, the semiconductor switch is switched on or off at a point in time at which no voltage or only a small voltage is present at the switch. In this case, the semiconductor switch must ideally accept no commutation current at all from other circuit sections, as a result of which, switch-on losses can be disregarded here. During the switch-off operation, care is taken to ensure that the voltage rise at the component is delayed in such a way that the maximum current density and the maximum voltage are not present simultaneously at the power switch at any point in time.
The basic construction and the method of operation of a circuit configuration for load-relieved switching that is designed as a PWM converter are described in detail in the article by Zaro et al. cited in the introduction. The circuit topology described by Zaro et al. in FIG. 1 therein includes a full bridge with four MOSFETs S1-S4 and an inductive element in the center of the bridge. What is problematic in this case is that, when very high powers will be switched, using conventional MOSFETs for such circuit topologies leads to the functional failure of the circuit.
This destruction mechanism will be illustrated with reference to FIGS. 9 and 10. FIG. 9 shows the temporal profile of the drain-source voltage VS2 at the MOSFET S2 and FIG. 10 shows a diagrammatic partial section through a vertical MOSFET that is typically used for this. The destruction mechanism is caused by an injection of storage charge into the drift region of the reverse-biased MOSFET S2, which is dissipated only very slowly (phase a). During a subsequent turn-off (phase b) of the MOSFET S2xe2x80x94for example after a few microsecondsxe2x80x94the storage charge still present in the volume of the drift region 110 leads to an excessively increased hole current (phase c) to the source terminal, which results in a voltage drop in the body zone 113 of the MOSFET. If the voltage drop VS2, at the instant tcrit, exceeds the switch-on voltage of a parasitic diode at the pn junction between the base zone and the drain zone, then the parasitic bipolar transistor that is always inherent in a MOSFET and whose emitter, base and collector are formed by the source zone 114, base zone 113 and drain and drift zone 110, 107 is undesirably switched on (phase d). This undesirable switch-on of the parasitic bipolar transistor is also referred to as the latch-up effect or the xe2x80x9csecond breakdownxe2x80x9d. In such a case, the reverse voltage of the semiconductor component falls very rapidly, which typically leads to the direct destruction of the semiconductor component itself. This latch-up effect is intensified by the fact that the voltage breakdown, promoted by the curvature of the pn junction between the base zone 113 and the drift zone 110, generally occurs at the edge of the base zone 113, since the hole current flows from the volume of the semiconductor body principally via the lateral pn junction into the base zone 113, so that the high current density arises there.
In the article cited in the introduction, Zaro et al. therefore arrive at the conclusion that semiconductor components in ZVS circuit topologies that have a high storage charge Qrr in the reverse operation and a correspondingly long recovery time trr are affected by precisely the destruction mechanism mentioned. FIG. 11 shows the temporal profile of the load current curve of a conventional MOSFET, which is used to define the storage charge Qrr and the recovery time trr. The storage charge Qrr results from:       Qrr    =                  ∫        t10        t20            ⁢                        Ir          ⁡                      (            t            )                          ⁢                  xe2x80x83                ⁢                  ⅆ          t                      ,
in other words the storage charge Qrr is the total quantity of the charge in the time period between t10 and t20. The instant t20 is produced by interpolating the straight line through the points Ir,90%=0.9 * Irrm and Ir,10%=0.1 * Irrm, where Irrm denotes the minimum load current Ir. The recovery time is then defined as:
trr=t20xe2x88x92t10.
In their article, the authors recommend that transistors with high storage charge Qrr and long recovery time trr not be used in ZVS circuit topologies, in particular in ZVS bridge circuits. This recommendation by the authors that is expressed in the cited article has been followed hitherto by manufacturers and customers of such circuit configurations, for example, those in the equipment industry for telecommunications products. The result is that nowadays power transistors with high storage charge Qrr and high recovery time trr are scarcely used in ZVS circuits.
One possibility for alleviating the destruction mechanism is to use semiconductor components in which irradiation is performed in order to reduce the charge carrier lifetime. On account of the recombination centers distributed in the space charge zone of the semiconductor component, this measure leads to faster discipation of the charge carriers injected into the drift zone even when no electric field is present. However, the irradiation destroys the semiconductor crystal, which adversely affects the on resistance RDSon, the blocking capability or the threshold voltage of the semiconductor component, depending on the type of irradiation. The impairment, i.e. the increase in the on resistance RDSon, should be avoided, however, particularly in the case of power components, since high on resistances result in a high power loss in the switched-on state of the semiconductor component. Furthermore, in the case of a short duration between the forward biasing of the current and its turn-off, it does not suffice, even with using the irradiation technique, to dissipate the storage charge contained in the drift zone in such a way that a latch-up effect as described above is avoided. Therefore, the irradiated semiconductor components mentioned are suitable only to a limited extent for ZVS circuit topologies that have to be designed for very high reverse voltages.
Thus, ZVS circuit topologies or ZVS bridge circuits which, on the one hand, are functional in the case of high storage charges and, on the other hand, also have an optimum on resistance have not existed heretofore.
It is accordingly an object of the invention to provide a circuit configuration for load-relieved switching which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide a functional circuit configuration, in particular a bridge circuit, for load-relieved switching whose power switches have an on resistance that is as low as possible.
Accordingly, circuit configurations for load-relieved switching of the generic type are provided which are characterized in that: at least one of the power switches is designed as a field-effect-controllable, integrated transistor operating according to the principle of charge carrier compensation, or the transistor has deep pn junctions.
By modifying the transistor structure, it is possible, according to the invention, first for the total quantity of storage charge present in the semiconductor body to be reduced, and second, for the current caused by the injection of holes to be conducted to an extent in a targeted fashion by the compensation structures. In this way, in the case of circuits equipped with the inventive compensation components, despite a high storage charge Qrr and a relatively high recovery time trr, which in the case of conventional MOSFETs would lead to the destruction of the MOSFET and thus to the functional failure of the circuit, this destruction mechanism is avoided. The experts"" prejudice, set forth in the article cited in the introduction, which describes the destruction mechanism of a conventional MOSFET when used in a full-bridge circuit, is refuted by the structural modification of the MOSFET. The structural modification can be effected first in providing power switches according to the principle of charge carrier compensation. The compensation components provided for this purpose are additionally distinguished, compared with conventional MOSFETs, by the fact that they have a very low on resistance RDSon, and consequently, significantly lower power losses in operation. Second, the structural modification can relate to providing power switches with deep pn junctions. Deep pn junctions are understood to be such structures when the extent of the body zone and regions coupled to the body zone, from the first surface of the semiconductor body to the drain region, amounts to more than 30% xe2x80x94preferably more than 45% xe2x80x94of the width of the space charge zone under an applied voltage. A compensation component is such a component with deep pn junctions, since the body region and the depletion zone of the same conduction type which is connected thereto typically extend into the semiconductor body even more deeply than 50% of the width of the space charge zone.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for load-relieved switching, that includes: a terminal for receiving a first supply potential; a terminal for receiving a second supply potential; a bridge circuit having at least two controllable power switches, the two controllable power switches having controlled paths configured in series with one another and between the first supply potential and the second supply potential, the bridge circuit having output terminals; a drive circuit for driving the two controllable power switches; and an inductive element connected to the output terminals of the bridge circuit. At least one of the two controllable power switches is designed as a field-effect-controllable, integrated transistor in accordance with a charge carrier compensation principle.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for load-relieved switching, that includes: a terminal for receiving a first supply potential; a terminal for receiving a second supply potential; a bridge circuit having at least two controllable power switches, the two controllable power switches having controlled paths configured in series with one another and between the first supply potential and the second supply potential, the bridge circuit having output terminals; a drive circuit for driving the two controllable power switches; and an inductive element connected to the output terminals of the bridge circuit. The two controllable power switches are designed as transistors with deep pn junctions.
In accordance with an added feature of the invention, each of the two controllable power switches is designed as an enhancement-mode MOSFET.
In accordance with additional feature of the invention, each of the two controllable power switches is designed as a MOSFET.
In accordance with another feature of the invention, the MOSFET is a vertical MOSFET.
In accordance with a further feature of the invention, the MOSFET has a controlled path defined by one of the controlled paths; and the MOSFET has an integrated diode and an integrated capacitive element that are connected in parallel with one another and with the controlled path of the MOSFET.
In accordance with a further added feature of the invention, the capacitive element is a capacitor having plates; and the capacitor has a high capacitance between 40 pF/mm2 and 100 pF/mm2 when a voltage of 25 V is present at the plates of the capacitor.
In accordance with another added feature of the invention, a semiconductor body is provided, and the field-effect-controllable, integrated transistor is configured in the semiconductor body. At least one compensation layer is configured in the semiconductor body. The compensation layer has at least one depletion zone of a first conduction type and at least one complementary depletion zone of a second, opposite conduction type. The depletion zone and the complementary depletion zone adjoin each other and form a deep pn junction. At least one body zone of the first conduction type is embedded in the compensation layer. At least one source zone of the second conduction type is embedded in the body zone. At least one gate electrode is provided for forming a current-carrying channel in the body zone when a gate potential is applied to the gate electrode.
In accordance with an additional added feature of the invention, the compensation layer has a plurality of depletion zones of the first conduction type and a plurality of complementary depletion zones of the second conduction type; the plurality of the complementary depletion zones have a total quantity of doping; and the plurality of the depletion zones have a total quantity of doping approximately corresponding to the total quantity of the doping of the plurality of the complementary depletion zones.
In accordance with yet an added feature of the invention, the compensation layer has a plurality of depletion zones of the first conduction type and a plurality of complementary depletion zones of the second conduction type; and the plurality of the complementary depletion zones and the plurality of the depletion zones are configured alternately next to one another in the compensation layer.
In accordance with yet an additional feature of the invention, the depletion zone adjoins the base zone.
In accordance with yet another feature of the invention, there is provided, at least one drain zone of the second conduction type. The drain zone is connected to the compensation layer. The complementary depletion zone has a doping concentration, and the drain zone has a doping compensation that is greater than the doping concentration in the complementary depletion zone.
In accordance with yet a further feature of the invention, a drift zone of the second conduction type is located between the drain zone and the compensation layer. The drift zone has a doping concentration that is less than the doping concentration of the drain zone.
In accordance with an added feature of the invention, a device for lifetime lowering is provided. The device is provided in the compensation layer or the drift zone. The device reduces free charge carriers.
In accordance with an additional feature of the invention, the device for lifetime lowering is designed as scattering centers or as radiation damage that is produced by irradiation or implantation.
In accordance with another feature of the invention, the bridge circuit is designed as a full bridge, and the bridge circuit has two further controllable power switches. The two further controllable power switches have controlled paths configured in series with one another and between the first supply potential and the second supply potential.
In accordance with a further feature of the invention, a transformer is provided that has a primary-side inductance. The inductive element forms the primary-side inductance of the transformer.
In accordance with a further added feature of the invention, the bridge circuit forms a switched-mode power supply, a pulsed power supply, a voltage regulator, or a lamp drive circuit.
In accordance with a concomitant feature of the invention, a transformer is provided that has a primary inductance, formed by the inductive element, and a secondary inductance. A primary-side circuit and a secondary-side circuit are inductively coupled by the primary inductance and the secondary inductance. The primary inductance is configured in the primary-side circuit. The secondary inductance is configured in the secondary-side circuit. The bridge circuit is for pulse switching power provided on the primary-side circuit to the secondary-side circuit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for load-relieved switching, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.